I'm fascinated by VHDL, though I'd consider myself a 'novice'.
I think something may be amiss with my board, or the wing.
I wrote some trivial 'hello world' VHDL, I made a component that I can "wire up" (technical term) to either the high side or low side of a wing. (The Papilio has 3 16 bit wing sockets, but the Button Wing is 8 bit, and can occupy either half of a wing).
So my component looks like this:
entity ButtonWing is
Button_01 : in std_logic;
Button_02 : in std_logic;
Button_03 : in std_logic;
Button_04 : in std_logic;
Led_01 : out std_logic;
Led_02 : out std_logic;
Led_03 : out std_logic;
Led_04 : out std_logic
architecture ButtonWing_arch of ButtonWing is
Led_01 <= '1' when Button_01 = '1' else '0';
Led_02 <= '1' when Button_02 = '1' else '0';
Led_03 <= '1' when Button_03 = '1' else '0';
Led_04 <= '1' when Button_04 = '1' else '0';
About as simple as it gets, each button is mapped to an LED. (I actually got a little too excited and started off with a much more complicated hello world that had me googling the language constructs, but I took a step back when I started see some weird behavior).
I can use this in my "main" top level entity to setup all hte ports this way, for testing. That looks something like:
architecture Behavioral of Main is
buttonWing : ButtonWing
port map (
Button_01 => W1A(1),
Button_02 => W1A(3),
Button_03 => W1A(5),
Button_04 => W1A(7),
Led_01 => W1A(0),
Led_02 => W1A(2),
Led_03 => W1A(4),
Led_04 => W1A(6)
buttonWing2 : ButtonWing
port map (
Button_01 => W1A(1+8),
Button_02 => W1A(3+8),
Button_03 => W1A(5+8),
Button_04 => W1A(7+8),
Led_01 => W1A(0+8),
Led_02 => W1A(2+8),
Led_03 => W1A(4+8),
Led_04 => W1A(6+8)
(and so on)
The W1A ports are defined in a file provided by the creators of the Papilio board, that take care of keeping straight what pins on the FPGA map to what pins on the Wings.
What I am seeing is that some of the LED's stay on, albeit dimly, when I push one of the buttons. If I push the button again, it lights up full brightness again.
It's late, I need to go to bed, so I'm not going any farther tonight. I have not yet tested all bit of all wings. But the ones I have tested lead me to think the problem is with the board, and not the Wing. Bummer.
I'll test the rest of it later, and follow up to this. Sweet dreams geeks.
Ok, I did some more testing, and I don't think the board is defective. I think what I am seeing is either 1) a quirk in FPGA's or Spartans in particular, or 2) my lack of understanding of the "Best practices" of VHDL and digital circuit design.ReplyDelete
I think it's not a busted board, and most likely some combination of the two things. I think I should make a new post to explain what I'm seeing better. Then I can send that post to my little brother, a self described "VHDL Ninja" for help :)